基于FPGA的802.3帧同步设计

基于GSM模块与CS1的实时采集系统下位机软件设计ABSTRACTIn the Synchronous communication systems,"synchronized"is the premise ofinformation transmission.For the recipient,simultaneously affect the processingsubsequent information,only by getting the correct frame synchronous to restore theframe information,further analysis of the frame structure,to obtain the informationthey need.Therefore,the frame synchronization is the prerequisite and basis forfollow-up data processing,the task of frame synchronization is to reign the basis ofthe synchronization information to identify the moment of the beginning and the endof frames of digital information.In the past few decades have been a lot of framesynchronization,one of the most common method of frame synchronization isperiodically insert a fixed-length header of frame synchronization code in thebeginning of a concentrated.Currently,the frame synchronization to achieve the maincorrelation method based on maximum likelihood (ML),similar to the natural ratiotest method.Around the hot topics of"FPGA-based 802.3 synchronous design "In this paper,based on the FPGA chip,through the research of 802.3 format to design the system ofbased on 802.3 FPGA synchronization.The System of research mainly by the designof the frame synchronization system,the FPGA simulation and implementation ofseveral aspects of composition of 802.3 synchronous.This paper first introduces the analysis of the practical significance of thesubject as well as Ethernet 802.3 format;Secondly,made a detailed study of the framesynchronization algorithm for VHDL language,then completed through VHDLlanguage based on FPGA hardware to 802.3 synchronous system;finally debuggingthe system to complete the task of the system and make the development on thesubject.The focus of the thesis is how to make 802.3 synchronization system basedon FPGA design tasks.-II