基于FPGA的MIPS指令设计与实现

广东东软学院本科设计（论文）ABSTRACTIn this paper,we will design a five level pipelined 32-bit CPU withMIPS architecture,which contains MIPS instruction set.The pipelinedarchitecture will be divided into five parts:instruction,decoding,execution,write back and storage.At the same time,we try to put forwardreasonable solutions to data conflicts,control conflicts and structureconflicts.Implement some instructions in MIPS instruction set.This design will use verilog-HDL (hardware description language),which is used to implement each module,simply put forward and solvesome data blocking problems in the pipeline,and use Modelsim to analyze,simulate and verify to complete the CPU design.Key words:Assembly line MIPS verilog-HDL ModelSimInstruction set