基于FPGA的查表式运算器的设计与仿真

AbstractThis article describes the design of a simple calculator,the designuses Field Programmable Gate Array FPGA based on VHDL hardware descriptionlanguage to design and Altera's Quartus II in software for emulation.Thissystem is componentted by the calculation section,storage section,display andinput section of the four parts,the computing part include adder,subtractor,multiplier and divider,Storage part needs three memory to help achieved:internal accumulator (acc),input register (reg)as well as the results ofregisters (ans).Display part is made up three decoder of 7 sections,respectively to show the number of input.Input part has ten number keys,from0 -9,also has addition and subtraction and multiplication and divisionarithmetic operator keys,a button and of equal sign and the clear key.Buttonscan be done through external within the four-digit'add','subtract','multiple',divede'the four kinds of functional operations,its structure is simple andeasy to implement.Key words:FPGA;VHDL;calclute